[FDE] SATA encryption in FPGA

[coderman]

On 1/23/07, Ven . <gvrtalks at hotmail.com> wrote:
> Any experts out there who have some advice on comparing IDE/SATA encryption
> implemented on an FPGA with building an ASIC for the purpose?

ASIC (like Padlock [0]) wins on efficiency and probably speed.  but an
FPGA array is certainly capable. [1][2]


> Also in the
> industry, is anyone willing to license their IP core for sucvh a purpose?

opencores is a good source, though i can't speak for the quality /
efficiency of the implementations. [3]


0. VIA Padlock Engine
   http://www.via.com.tw/en/initiatives/padlock/hardware.jsp

1. Cost-Optimized Parallel COde Breaker
   http://www.copacobana.org/

2. NALLATECH FPGA Computing Modules
   http://www.nallatech.com/?node_id=1.2.1&id=3

3. OpenCores Crypto
http://www.opencores.org/browse.cgi/filter/category_crypto