[FDE] Sony to present CLEFIA at Fast Software Encryption (Ali, Saqib)

[Robert Wann]

The limited amount of information on the CELFIA pages only disclosed it is
similar to AES but failed to explain how the S-Box, key schedules, and mode
of operation are done. Or perhaps I overlook some details.

The 1.42Gbps throughput under 90nm (nano meter, 0.09 micron) semiconductor
with 6.1K logical gates maybe impressive but also fails to address:

1. what's the key length under this throughput and gates count;
2. does this reported gates include any key registers?;
3. what's the mode of operation under this throughput and gates count.

On AES, the bandwidth limitation shall mainly reside on how the interface is
implemented; what's the key length; and what's the mode of operation. It's
obvious from the mathematical point of view, the longer key length requires
longer computing cycles. Likewise, CBC's implementation is a bit harder than
that of the ECB mode of operation.

In short, the reported result of 1.42Gbps under 90nm with 6.1K gates count
will not be impressive if that's not done using 256-bit key length and CBC
mode of operation.

Enova Technology's latest SATA AES technology
(http://www.enovatech.net/products/mx_info.htm) is able to produce up to
1.5Gbps with 7.5K gates under much less expensive 0.18 micron semiconductor
process.

Thanks,
Robert Wann
Enova Technology

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Sent: Saturday, March 24, 2007 2:00 AM
Subject: FDE Digest, Vol 6, Issue 18


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>    1. Sony to present CLEFIA at Fast Software Encryption (Ali, Saqib)
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> Message: 1
> Date: Thu, 22 Mar 2007 20:08:36 -0700
> From: "Ali, Saqib" <docbook.xml at gmail.com>
> Subject: [FDE] Sony to present CLEFIA at Fast Software Encryption
> To: FDE at www.xml-dev.com
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> Sony and  Nagoya University will be presenting paper about CLEFIA at
> the Fast Software Encryption (FSE) 2007 in Luxembourg . CLEFIA is a
> The 128-bit Blockcipher that is efficient and open.
>
> "The key advantages of "CLEFIA" are its enhanced implementation
> efficiency in terms of both hardware and software, and its high speed
> operation. When implemented in hardware it achieves maximum throughput
> of 1.42 Gbps using a 0.09 ?m CMOS standard cell library and gate size
> of just 6.1K, representing the world's highest hardware gate
> efficiency. Consequently, "CLEFIA" is able to provide advanced
> capabilities, even in restrictive environments such as smart cards and
> mobile devices."
> Complete Story at: http://www.huliq.com/16091/sony-develops-clefia
>
> More info about FSE:
> http://fse2007.uni.lu/accepted.html
>
>
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